This invention relates to methods of forming capacitors on a wafer, to photolithographic methods of forming capacitors on a wafer, and to semiconductor wafers.
Memory circuitry in semiconductor fabrication is formed to include an array area where individual memory cells are typically fabricated in a dense repeating pattern, and a peripheral area where peripheral circuitry which is operatively configured to write to and read from the memory array is fabricated. Peripheral circuitry and array circuitry are typically largely fabricated at the same time. Further the memory cell capacitors within the memory array are commonly fabricated to be vertically elongated, sometimes in the shape of cups or containers, in order to maximize the available surface area for individual capacitors for storage capacitance. The electronic components or devices of the peripheral circuitry are not typically as vertically elongated, thereby creating topography problems in the fabrication due to portions of the memory array circuitry being fabricated significantly elevationally higher than portions of the peripheral circuitry.
The invention includes methods of forming capacitors on a wafer, photolithographic methods of forming capacitors on a wafer, and to semiconductor wafers regardless of the method of fabrication. In one implementation, A method of forming capacitors on a wafer includes forming a dielectric well forming layer over the wafer. A protective rim is formed over the well forming layer proximate to and along at least a portion of the wafer""s peripheral edge. Portions of the well forming layer are removed radially inward of the protective rim to form a plurality of wells within the well forming layer. A plurality of capacitors are formed within individual of the plurality of wells.
In one implementation, a semiconductor wafer includes a peripheral edge extending all about the wafer. An insulative layer is received over the semiconductor wafer and extends to proximate the wafer peripheral edge. The insulative layer includes a peripheral rim portion proximate to and extending about at least a portion of the wafer peripheral edge. A plurality of wells are formed in the insulative layer. Individual of said insulative layer wells include a plurality of capacitors. The peripheral rim portion is void of any of said insulative layer wells.